This invention concerns silicon-based integrated circuits, using CMOS (metal oxide semiconductor) technology, i.e. basically comprising field-effect transistors with control grids insulated by an oxide.
This technology is used in linear amplifiers. However, if an increase in the available output power is needed, there has to be a limitation, first on the output impedance (too high for MOS transistors, for example if a standardized 600 Ohm load is to be supplied), and second on the dimensions of the output transistors in the integrated circuit: for same output current, an MOS transistor takes up more room than a bipolar transistor.
It would therefore be an advantage for the amplifier output stage to contain bipolar transistors, and this is in fact possible using CMOS technology: the resulting integrated circuit then comprises both bipolar transistors and MOS field-effect transistors.
Consideration might be given to the conventional use of an output stage with two NPN and PNP bipolar transistors, in a push-pull assembly, to make the amplifier function in class B or AB, namely with sufficient linearity, and also with an operating current when at rest that is either 0 (for class B), or low enough not to produce excessive losses (for class AB).
Unfortunately, only NPN bipolar transistors can be mounted with MOS transistors on the same substrate. There is no simple way to obtain a PNP transistor and an NPN transistor with symmetrical characteristics, for push-pull mounting, in MOS technology.